Line adapter for data communication system

ABSTRACT

THERE IS DESCRIBED AN ADAPTER FOR CONNECTING THE INPUTOUTPUT BUFFER OF A PROCESSOR TO A STANDARD TELEPHONE DATA SET FOR TRANSMISSION BETWEEN THE PROCESSOR AND A NUMBER OF REMOTE TERMINALS. THE ADAPTER PERMITS AUTOMATIC POLLING OF A NUMBER OF REMOTE STATIONS USING POLLING INFORMATION STORED IN THE INPUT-OUTPUT BUFFER BY THE PROCESSOR WITHOUT INTERVENTION OF THE PROCESSOR. THE ADAPTER PROVIDES TRANSLATION BETWEEN THE INTERNAL SIX-BIT CODE OF THE PROCESSING SYSTEM AND A STANDARD ASCII SEVEN-BIT CODE FOR TRANSMISSION TO OR RECEPTION FROM THE REMOTE TERMINALS. THE ADAPTER IS A SYNCHRONOUS IN ITS OPERATION.

R. l.. RAwLlNGs ETAL 3,559,184

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United States Patent Oiiice 3,559,184 Patented Jan. 26, 1971 U.S. Cl.S40-172.5 9 Claims ABSTRACT OF THE DISCLOSURE There is described anadapter for connecting the inputoutput buffer of a processor to astandard telephone data set for transmission between the processor and anumber of remote terminals. The adapter permits automatic pollving of anumber of remote stations using polling information stored in theinput-output bulTer by the processor without intervention of theprocessor. The adapter provides translation between the internal six-bitcode of the processing system and a standard ASCII seven-bit code fortransmission to or reception from the remote terminals. The adapter isasynchronous in its operation.

In Pat. 3,390,379, assigned to the same assignee as the presentinvention, there is described a data communication system by which adata processor may communicate with a number of remote terminal units ofdifferent types. Specifically, there is described a terminalcommunication control circuit which acts as a butler between a processorand a number of remote terminal stations. Each communication linkrequires a line adapter which controls the transfer of data between theterminal communication control and the communication lines to thevarious remote stations.

The present invention is directed to an improved line adapter forconnecting the data transmission terminal to a standard data set, suchas a Western Electric 202 data set.

In brief, the adapter of the present invention is asynchronous inoperation for use with standard telephone circuits. The adapter permitsthe transmission of a number of different polling messages to selectedremote stations via the telephone communication link. Each pollingmessage polls a particular remote station to initiate transmission ofdata from the remote station to the inputoutput buffer of the centralprocessor. As each polling message is transmitted, the adapter waits toreceive a response, and if the response is negative, the adapter causesthe next polling message stored in the buffer memory to be sent. If apositive response is received, the adapter causes the received messageto overwrite the polling messages in the buffer memory. The adapterprovides the necessary code translation to permit use of substantiallythe full seven-bit ASCII code to be used in the communication link, theadapter providing translation to the internal six-bit code of theprocessor. The polling messages are recycled automatically until apositive response from a polled station is obtained or until polling isinterrupted by an interrogation from the processor.

DESCRIPTION OF THE DRAWINGS For a better understanding of the invention,reference should be made to the accompanying drawings, wherein:

FIG. l is a block diagram of the data transmission system to which thepresent invention is utilized;

FIG. 2 is a block diagram of the Data Transmission Terminal unit showingthe interface with the line adapter;

FIG. 3 is a block diagram of the Data Set showing the interface with theadapter;

FIG. 4 is a diagram summarizing the operation of the line adapter;

FIG. 5 shows the code set for use with the remote stations.

FIG. 6 is a block diagram of the adapter logic in the transmissionstate;

FIG. 7 is a block diagram of the adapter logic in the receive state; and

FIGS. 8 through 14 are timing diagrams useful in describing theoperation of the adapter.

DESCRIPTION OF A SPECIFIC EMBODIMENT The present invention is directedto a line adapter useful in a system such as shown in FIG. 1 forproviding data communication between a computer 10, such as theBurroughs B-5500 computer, and a plurality of remote terminal stations,as indicated at 12, which may be the Burroughs TC-SOO Data CommunicationProcessor described in copending application, Ser. No. 723,088, filedApr. 22, 1968. Buffering between the computer 10 and the remote stationsis provided by a Data Transmission Terminal unit (DTT) 14 which isdescribed in U.S. Pat. 3,390,379. The line adapters, two of which areindicated at 16 and 18, hereinafter described in detail, provide controlof data between the Data Transmission Terminal unit 14 and standardtelephone data sets indicated at 20, such as the Western Electric 202.The data set provides serial transmission on standard telephone lines bya modulated carrier at bit rates of 600 to 1800 bits per second.

The interface between the line adapter 16 and the data set 2t] is shownin FIG. 3. Binary information is transmitted to the telephone line byswitching the level on the BA input line between i6 volts. Communicationwith the remote terminal requires that a level be raised on the CD rinput which places the communication link in a ready condition. When itis desired to transmit data to the line, the level is raised on the CAinput indicating to the communication link that there is a request tosend data. When the data set is ready to either receive or transmitinformation, it raises the level on the CC line and it raises the levelon the CF line, indicating that the carrier signal is on the line. Whenthe data set is clear to send data, it raises the level on the CB outputline. Received binary data changes the level on the BB output linebetween i6 volts.

The interface between the line adapter 18 and the Data TransmissionTerminal unit 14 is shown in FIG. 2. While the interface of the DataTransmission Terminal is described in detail in the above-identifiedpatent together with a description of the operation of the unit, a briefreview of the significance of a number of these signals and the basicoperation of the terminal unit is believed in order to better understandthe present invention. The DTT unit 14 includes a buler memory 26 whichis divided into a number of separate addressable planes, indicated asrows in the block diagram. Each plane has its own associated lineadapter which is designated by the address in an vS- address register45. This address is decoded by an S-decoder 46 and applied to theinterface at the output line designated ADH. The AD line designateswhich line adapter is to be put into operation. The address designatinga memory plane and the associated line adapter is normally received fromthe processor and placed in an input or AC register 47 which alsoreceives data from the designiated line adapter through informationinput lines designated ACH.

The buffer memory 26 is arranged in a plurality of separately adressablecolumns starting with address 00. Column addressing is through anX-register 38. The 00 column is used to store the address of the nextcharacter location within the buffer which is to be transmitted or inwhich the last received character has been stored. The

address column 01 is used as a temporary input-output storage bufferwhere a character is placed before it is released for transmission tothe communication line or where it is initially received from the datacommunication line.

All communciation with the memory 26 is through an information register36 which stores one word of information corresponding to two six-bitcharacters, the standard character length for the B-5500 computer 10.Data is transferred from the information register 36 either serially orin parallel, a character at a time. Information data in the register 36is transferred to the line adapter over output lines designated DCD, theDCE line being used for Serial transmission. Operation of the DTT unit14 is by a central control circuit 22 which is synchronized from a clocksource which generates control clock pulses (CCP) at clock rates at, forexample, 10 microseconds.

In the course of transmitting or receiving data, the DTT unit 14provides a number of control signals to the line adapter 16 includingthe clock pulses CCP, a start level STR, and the adapter designationaddress on lines ADn.

Other signals at the interface include the output line CAT. This is aZO-microsecond pulse normally generated by the DTT unit 14 when a fullcharacter is stored in the information register 36 and is available foraccess by the adapter. The output line CWT is a l-microsecond pulseindicating the second half of the CAT time. The output line BAT is al0-microsecond pulse indicating bit access time to the adapted. Singlebit transfer between the information register 36 and the adapter is overthe ACE and the DCE lines at BAT time.

In addition, the DTT unit 14 receives a number of control signals fromthe line adapter. The manner in which these signals are generated willhereinafter be described in more detail. The TRS input line provides asignal indicating that the line adapter is in either the transmit stateor in the receive state. The ANN input line indicates that the adapterneeds attention, and the BSn lines identify which buffer needsattention. The CAM input provides a level indicating that the adapterwants to transfer a character in parallel to the information register36. The ARC input indicates that a character is to be replaced in thebuffer, while the DIC input indicates that a character is to bediscarded. The RES line is a reset signal input. The EIR line signalsthat the buffer recognizes the end of an input, while the EOT linesignals the end of transmission. The BKC line provides a back-spaceoperation which is used during transmission to increment the columnselect address in the register 38 while discarding the previouscharacter.

The B-5500 computer uses six-bit characters, permitting 64 differentcharacters, whereas the data transmission terminal operates on aseven-bit code known as ASCII. The code set for the adapter using theASCII code is set forth in FIG. 5. It will be noted that the seven-bitcode in which the characters are received or transmitted by the lineadapter have four columns in which the sixth and seventh bits are equal.These characters are referred to as the control state characters. In theremaining four columns, the sixth and seventh bits are unequal. Thesecharacters are referred to as the text state characters. The internalsix-bit code set for the B5500 computer corresponds to columns 2, 3, 4,and except that the Circumex character of ASCII is an Unequal (7e)character in the six-bit code while the Underline character is a GroupMark (e) character in the six-bit code.

The adapter has a ip-op which determines whether the adapter is in thecontrol state or in the text state. A change of state is signaled by thepresence of a 7e character (011110) during transmit. During receive, achange of state is signaled by the sixth and seventh bits of a characterbeing equal when the adapter is in the text state and being unequal whenthe adapter is in the control state. In the control state, any six-bitcharacter in columns 4 and 5 (FIG. 5) is changed to the character in thesame row of columns 6 and 7, while the character in column 2 and 3 mapto the Characters in columns 0 and 1. This is accomplished by alwayscomplementing the sixth bit and making the seventh bit equal to thesixth bit when transmitting, or complementing the sixth bit andstripping off the seventh bit when receiving. Since the 7e character(011110) in the internal six-bit code maps to the Tilde character in theASCII code, the character cannot be transmitted and is discarded ifreceived. Also the Group Mark (011111) is used in the adapter to signala control condition and so the corresponding ASCII code characters andDelete (DEL) are not transmitted and are discarded if received. Specialprovision is made to transmit and receive the Circumllex character bytranslating it to a pair of characters.

Before considering the operation of the adapter circuit in detail, anoverall summary of the operation of the adapter under various operatingconditions can best be understood by reference to FIG. 4 which shows anoperational chart of the adapter. Initially, the adapter is in an idlecondition, represented by I at 50. When the DTT buffer is loaded, theDTT unit 14 sends over an STR signal to the designated line adapter 16.This causes the line adapter to enter the transmit mode as indicated at52. The line adapter then examines the character on the DCn lines fromthe information register 36 to determine what character is present. Ifthe DTT unit is arranged to poll a number of remote stations over acommon telephone line through the selected or designated adapter, thebuffer memory at this time will be loaded with a sequence of pollingmessages.

The series of polling messages stored in the buffer memory each consistsof an EOT character followed by two address characters, a POL character,and an ENQ character. The EOT character insures that the adapter iscleared and in the idle state. The two address characters identify theremote station being polled and set the particular remote station toreceive the POL character. The ENQ character signals a remote stationthat a response is required. Thus, the polling message operates to seekdata from a selected remote station.

Returning to the operation summary of FIG. 4, after entering thetransmit state, the adapted looks at the first character placed in theinformation register 36 by the DTT unit. If this is an EOT character, asindicated at 54, the character is sent to the remote station, asindicated at 56. Remembering that an EOT is being sent, the adapterlooks at the next character in the buffer to determine whether or not itis a Group Mark, as indicated at 58. The Group Mark (011111), if presentin the buler, is not transmitted, as indicated at 60, and the system isplaced in an idle-interrupt condition 62. Thus, the Group Mark followingan EOT is used to interrupt a transmission.

When polling, the next two characters after the EOT in the pollingmessage from the buffer are address characters. These two addresscharacters are transmitted in the normal manner, alerting the selectedremote station. If a POL character is next encountered in the bufferfollowing the two address characters, as indicated at 64 in FIG. 4, thePOL character is sent to the remote station, as indicated at 66, and theline adapter enters a poll state of operation, as indicated at 68. Theadapter now looks for the ENQ character signaling the end of the pollmessage. If the ENQ character is not sensed in the buffer at this time,as indicated at 70, the line adapter is returned to the idle state, asindicated at 72.

Assuming that the next character is an ENQ, it is sent to the remotestation, as indicated at 73, and the adapter enters a receive state, asindicated at 74. The line adapter now waits for a response from theremote station. A twosecond timer is set, as indicated at 76. If thistimer times out before any response is received back from the remotestation, a special Interrupt is sent by the adapter to the system, asindicated at 78.

Normally, the remote station will come back either with an EOTcharacter, indicating a negative response to the poll, or it will comeback with a message. If it comes back with an EOT character, asindicated at 80, the character is discarded and not stored in the bufferand the adapter returns to the transmit condition, as indicated at 82.Operation then continues with the transmission of the next pollingmessage in the buffer unless the next character encountered in thebuffer is a Group Mark, as indicated at 84. If it is a Group Mark, it istested to see whether it is a text Group Mark or a control mark, asindicated at 86. If it is a text Group Mark, the Group Mark is precededby a ,f character to ag a change to the text state of the adapter. Thebuffer address in the DTT unit is then reset, and the polling isrepeated. If it is a control Group Mark, a special Interrupt is sent tothe system and the line adapter is returned to the idle state.

Other special characters which may be sensed during the transmitcondition are the ETX character, signaling the end of a text, the ENQcharacter, which is used to signal the end of a selection message aswell as a poll message, or the Group Mark character. If either the ETXor ENQ character is sensed by the adapter, as indicated at 92, it issent to the remote station, as indicated at 94, and the line adapterenters the receive condition, as indicated at 96. The Group Mark alsocauses the adapter to enter the receive state but it is not sent to theremote station.

Again the timer is set, and, if nothing is received within two seconds,the Interrupt is set. Otherwise the line adapter begins to receivecharacters from the remote station. These are loaded into the bufferuntil either an ETX or an EOT character is encountered, as indicated at100 and 102. The ETX character, when sensed by the line adapter. resultsin an Interrupt condition and a reset signal being sent to the DTT unit,as indicated at 104. lf an EOT character is sensed, a diterent Interruptand a reset are sent to the DTT unit, as indicated at 106. The lineadapter then returns to the idle state. If no character is received, thetimer circuit will time out, as indicated at 108, and an Interrupt isalso set, as indicated at 110.

Referring to FIG. 6, there is shown in block diagram form theoperational logic of the line adapter in the transmit state. In thefigures, all flip-flops are activated in synchronism with the clockpulses CCP from the DTT unit 14 unless otherwise indicated. AND circuitsare indicated as a circular segment with a dot, while OR circuits areshown as segments of a circle with the input lines extending through thesegment of the circle. Other logical circuits will be described as theyare encountered. Rather than connecting up all the logical elements ineach figure. input and output lines of each ip-op and its control logicare labeled. If followed by an apostrophe or prime indication appendedthereto, such a line will be true whenever the line accompanied by thesame label Without an apostrophe is false" and vice versa.

Referring to FIG. 6, the control logic for the start of transmission bythe line adapter is shown in detail. The timing diagram of FIG. 8 isuseful in understanding the operation of the adapter in startingtransmission of a character to the remote station.

Operation is initiated by the DTT unit 14 which provides a start pulseon the STR line and provides an address on the ADn lines. A decoder 112looks at the address and if it corresponds to the particular lineadapter, a DES output level is changed from false to true. While notspecifically shown, the DES level is applied throughout the controllogic of the line adapter to place the line adapter in an operativestate.

The STR is applied to a Transmit ip-op 114 (TRSF) causing the TRS outputlevel of the flip-flop to go true, indicating the adapter is in thetransmit state. The TRS output is applied to the CA line (data setinterface) to activate the data set. The STR pulse also turns on theAttention-Needed tiip-tiop 116 (ANNF) providing a true level on the ANNoutput to the DTT unit 14. This signals an attention-needed conditionfor the line adapter. With both TRS and ANN lines true, the DTT unit 14initiates an output operation in the DTT unit in the manner described indetail in the above-identified Pat. 3,390,379. The DTT unit 14 transmitsa pulse on the BAT line. The initial BAT pulse occurs before the fIrstcharacter is available in the information register of the DTT unit 14.Therefore, a reset signal is applied to the RES line in response to theinitial BAT pulse. This is accomplished by an AND gate 118 to which theBAT pulse is applied together with the TRS level from the transmit ip-op114 and a LOC' level from a LOCF flip-fiop 120, which is initially inthe zero state. The reset signal on the RES line forces the DTT unit 14to generate a CAT pulse and C WT pulse.

A BITF liip-flop 122 controls the level on the transmitted data line BAto the data set. When the adapter goes into the transmit state, the BITFfiip-fiop is set to l by the output of an AND circuit 124 when the TRSline goes true and the LOC' line is true. After some delay, the data setindicates that the communication link is clear to send by providing atrue level on the CB line from the data set. This is used to turn on anadapter clock 126 in response to the output of an AND circuit 128 whichsenses when the TRS line and the CB line are both true. The adapterclock generates clock pulses at the required bit rate of the data set.The adapter clock pulses appear on a line labeled ACLP. These pulses areapplied to the BITF Hip-flop 122. The rst ACLP pulse turns on the LOCFtiip-op in response to the output of an AND circuit 128.

The first ACLP turns on a SANF flip-flop 130 which in turn causes theANNF flip-flop 116 to be turned on" by the next CCP clock pulse. TheANNF Hip-hop 116 again signals the DTT unit 14 to initiate an output tothe adapter. The next BAT pulse received by the adapter turns oit theAiNNF iiip-op 116. The BAT pulse also signals that the first bit of thecharacter to be transmitted is present on the DCB line from theinformation register 0f the DTT unit 14. This first bit is used to setan NBTF flip-flop 132 to either the 0 or l state in response to theoutput of either an AND circuit 134 or an AND circuit 136. Thus, thebinary value of each bit of the character to be transmitted is set inthe NBTF Hip-flop 132 during the next succession of BAT pulses. The NBTFflip-flop, in turn. controls the BITF flip-Hop 122, the latter being setto either 0 or l by the next adapter clock pulse ACLP when the adapteris in the transmit state, as controlled by the output of AND circuits133 and 135. As shown in FIG. 8, successive BAT pulses cause successivebits of the character to be put on the line to the data set including aStart bit, seven information bits, a Parity bit, and a Stop bit.

After the last bit is transferred, the DTT unit 14 ptits the nextcharacter stored in the buffer into the information register and putsout a CAT pulse. The CAT pulse is divided into two parts, the secondpart being identified by a CWT pulse. During the first portion of theCAT pulse, the adapter determines what six-bit character is present inthe information register of the DTT unit 14 and adds the appropriateseventh bit according to code set shown in FIG. 5 if the adapter is inthe control state. The DIT unit at this time adds the Start, Stop, andParity bits and if the adapter is in the text state, makes the seventhbit opposite to the sixth bit. During the second half of the CAT pulse,i.e., CWT time, the adapter takes appropriate action depending upon whatfull sevenbit character is now present in the information register 36.An AND circuit 138 senses the CAT pulse, the CWT' level, and the TRSlevel. The output of the AND circuit is labeled DTCD and is true onlyduring the lirst half of the CAT pulse when the line adapter is in thetransmit state. An AND circuit 140 senses the CWT pulse during 7 thetransmit state, producing an output DTWS only during the second half ofthe CAT pulse.

With the first six-bit character of the polling message in theinformation register 36 of the D'IT unit 14, it is necessary to convertthis to a corresponding seven-bit code character. A text Hip-hop 142(TEXF) determines whether the adapter is in the control state or textstate. At the start, the TEXF ip-op 142 is otff indicating the controlstate. An ENDF flip-flop 144 is a control ipiiop indicating whether ornot the adapter is in condition to end transmission and at the start isolif The DCn lines from the DTT unit 14 are applied to a decoder 146,which decodes the character and the information register of the bulTermemory. If the six-bit character is a 7e character, the decoder providesa true level on an output labeled DNE; if the character is a Group Mark.the decoder provides a true level on an output labeled GMK. If neithercharacter is present, the character is converted to seven bits. This isaccomplished by a logical AND circuit 148 which senses the DTCD level,indicating that it is the first half of the CAT pulse and the buffer isin a transmit state (TRS). The AND circuit 148 also senses that thc TEXFflip-[iop 142 is in the control state TEX and that the ENDF flip-Hop 144has not been turned on, as indicated by line END'. The AND circuit 148also senses that the character to bc transmitted is not a Group Mark, asindicated by the GMK level and that the character is not a #L character,as indicated by the DNE' level. Neither of these latter two charactersis transmitted to the remote stations but are used to flag the lineadapter to change from a control to a text state, or a text to a controlstate. in the case of the character, and to terminate transmission inthe case of the Group Mark character.

The output of the AND circuit 148 is applied as an ARC signal to the DTTunit 14 to signal that the character is to be replaced. It is alsoapplied to an AND circuit 150 for gating the DCI through DC5 lines tothe AC1 through AC5 lines. Thus, the iive least significant bits arerestored in the information register 36 in the DTT unit 14. At the sametime, the output of the AND circuit 148 is applied to a gate 152 whichgates the DC'S level to both the ACG and ACq lines. Thus, the inverse ofthe DCS line is applied to the ACE line, and the ACS line and AC7 linesare made equal. This corresponds to the mapping change indicated by FIG.5 in which a six-bit character from columns 4 and 5 is changed to aseven-bit character of columns 6 and 7, and a six-bit character ofcolumns 2 and 3 is changed to a seven-bit Character of columns 0 and 1when the adapter is in the control state. The Start, Stop, and Paritybits are added to the characters by the DTT unit 14 so that the fullcharacter is ready to send out on the telephone lines by the data set.

Assuming that a polling message is to be transmitted, the full characterto be transmitted at this time is EOT. The waveforms of FIG. 9 show theoperation of the adapter logic element during transmission of thepolling message. During the second half of the CAT time, an EOT linefrom the decoder 146 is true and the DTWS level goes true. During thistime, a control flip-flop 154 (EOTF) is turned on by the output of anAND circuit 156, which senses the DTWS time, that the ENDF tiipflop 144is 05, and that the EOT output of the decoder 146 is true, indicatingthat the EOT character is present. When the EOTF ip-tiop 154 is on, itturns on a control Hip-Hop 158 (SELF) in response to the output of anAND circuit 160 which senses that the EOTF level is true and that theTRS level is true, indicating that the adapter is in the transmit mode.The ten bits of the EOT character are now transmitted during successiveBAT pulses. The DTT unit then loads the next character in theinformation register and generates the next CAT pulse. This is normallythe first address character of the polling message. At the start of CATtime, the EOTF hip-flop 154 and SELF ip-op 158 are turned "ott" by theoutput 8 of an AND circuit 162 to which the DTCD level is applied,indicating the first half of the CAT pulse, the GMK' line from thedecoder 146, indicating that the character is not a Group Mark, and theEND line, indicating that the ENDF flip-flop 144 is ott Otherwiseoperation is identical to that described above.

When the POL character is encountered after the second address characterhas been transmitted, the SELF flip-flop 158 is turned on" hy the outputof an AND circuit 164. which senses the DTWS level during the secondhalf of CAT time, the POL level from the decoder 146, indicating that aPOL character is present, and the END' level, indicating that the ENDFip-op 144 is olf The SELF ip-op 158 being on together with the EOTF{lip-flop 154 being ott indicates to the line adapter that it is now inthe poll state. The POL character is then transmitted in the normalmanner and the next character in the poll message is examined during thenext CWT time. This should be the ENQ character which signals an inquiryto the remote terminal.

During CWT time for the ENQ character, a timing fiip-tlop 166 (TIMF) isturned on by the output of AND circuit 167 in response to the ENQ levelderived from the decoder 146, together wtih the DTWS signal. This, inturn, puts the ENDF flip-flop 144 in the l state in response to theoutput of an AND circuit 168 to which the TRS level and the TlM levelare applied. The ENQ character is transmitted in the manner describedabove.

At the next CAT time, the LOCE ip-op 120 is turned "off" by the outputof an AND circuit 170 to which the DTWS level, signifying the secondhalf of the CAT time, and the END level, indicating that the ENDFflipflop 144 is turned on, are applied. The TRSF iiip-tlop 114 is thenturned o to put the adapter in the receive state. This is accomplishedby the output of an AND circuit 172 that senses that the ENDF flip-flop144 is on and that the LOCF Hip-flop 120 is off A delay, indicated bythe delay circuit 174, is provided between the AND circuit 172 and theTRSF Hip-flop 114. This delay is normally of the order of four adapterclock pulse periods and is provided to permit the data set to completetransmission of the ENQ character. The output of the delay circuit 174also resets the ENDF flip-flop 144. When TRSF 114 is turned oli, theadapter clock is stopped. Since no characters are to be transmittedfollowing the ENQ character, a discard signal DIC is sent to the DTTunit 14 at each subsequent CAT time. This is generated by the output ofan AND circuit 176 to which the DTCD level is applied during CAT timeand to which the END level is applied. The DIC level prevents thegeneration of BAT pulses, but rather a CAT pulse is generated at thenext adapter clock time in response to the attention-needed signal ANN.Thus, no further characters are transmitted during the delay period untilthe TRSF iiip-op is turned ott This completes the transmission of thepoll message to the remote station and the adapter returns to thereceive state. However, the adapter remains in the poll state in whichthe SELF Hip-op 158 is on. The line adapter now awaits for a responsefrom the remote station. The adapter logic for the receive stateoperation is shown in FIG. 7. The waveforms of FIG. 10 show theoperation of the adapter during the receive state. It should be notedwith TIM true, a two-second timing circuit 169 is turned on by theoutput of an AND circuit 171. The AND circuit also senses that the CHRFHip-flop 178 is off The latter tiip-iiop is turned on when a characteris being received, so that the timing circuit 169 is turned ott if acharacter is received within two seconds. Otherwise the circuit 169times out, producing an Interrupt signal.

The response from the remote station may be an EOT character, indicatinga negative poll response, or it may be a message. In either case, withthe data set turned on, the BB line and the CF line from the data setare true. When a Start pulse at the beginning of a character is receivedon the line by the data set, the BB line goes false and the BB' line,provided by an inverter 175, is true. This turns on the adapter clock126 through an AND circuit 176 which senses that the BB line is true,the LOC' line from the LOCF ip-flop is true, and that the TEX' line fromthe TEXF flip-Hop is true. This starts the adapter pulses ACLP after adelay interval of a half pulse time. The first adapter clock ACLP turnson a CHRF flip-Hop 178 in response to the output of an AND circuit 180which senses that the adapter is in the receive state as indicated bythe TRS' line.

The BITF flip-Hop 122 is controlled by the information levels on the BBline from the data set during successive adapter clock pulses. The BB'line and the BB line are applied respectively to AND circuits 180 and182 together with the CF line, indicating the presence of a carrier, andthe TRS line, indicating the receive state of the adapter. The output ofthe AND circuit 180 sets the BITF flip-Hop 122 to the 0 state while theoutput of the AND circuit 182 sets it to the l state. The bits stored inthe BITF ip-op 122 are transferred to the DTT unit over the ACS linesthrough AND circuits 184 and 186, which sense that the adapter is in thereceive state. The DTT unit 14 is alerted to receive data by the TRSline, which is false, indicating that the adapter is in the receivestate, and by the attention-needed signal on the ANN line. The ANN lineis turned on by each adapter clock pulse and turned off by each BATsignal received back from the DTT unit 144, in the manner alreadydescribed above.

After all of the bits of the first character are received, the DTT unit14 generates a CAT pulse and a CWT pulse. An AND circuit 188 senses theCAT pulse and the CWT condition and the T RS condition, producing a DRCDoutput when the adapter is in the receive state and during the firsthalf of the CAT pulse. An AND circuit 190 senses the TRS condititon andthe CWT pulse, producing a DRWS pulse on the output during the secondhalf of the CAT pulse.

During CAT time, the adapter responds to the full character now storedin the information register and applied to the decoder 146 over the DCnlines. The resulting operation is shown by the waveforms of FIG. 11. TheEOT character, if present at this CAT time, indicates a negative pollresponse, which must be discarded and the adapter returned to thetransmit state for transmitting the next poll message. A discard signalDIC is produced by the output of an AND circuit 192 which senses thatthe EOT character is present by the EOT line from the decoder 146 andthat the adapter is in the poll state as determined by the EOTF line andthe SELF line. The transmit ip-op 114 is then turned on by the output ofan AND circuit 194 to which the DRWS signal is applied and also pollstate signals EOTF' and SELF. The output of the AND circuit 194 alsoturns on the ANNF flip-flop 116, signaling attention-needed to the DTTunit 14. This restarts the transmit operation described above inconnection with FIGS. 6 and 8. The CHRF ip-op 178 is turned olf at DRCDtime by the output of an AND circuit 195 which senses that BIT is true,indicating the end of the character, and SCI is true, indicating that nomode change from text to control state or control to text state ispresent.

When the adapter is in the receive state and in the polling state, assensed by an AND circuit 197, it sends a back-space signal BKC to theDTT' 14. The DTT unit 14 at CAT' time and with BKC true, causes the X,Y, and Z registers to be reset to the initial information storageaddress of the buffer, excluding the address storage location and theinput-output storage location for the buffer. As a result, the firstcharacter received from the remote station, if it is not a negativeresponse EOT, is stored in the start of the data storage portion of thebuffer. However, in the event an EOT character is received andrecognized during CAT time by the decoder 146, the discard signal on theDIC line at the output of the AND circuit 192 prevents the address inthe X, Y, and Z registers from being stored in the address buffer atmemory column 00. See the description in the above-identified Pat.3,390,379. Therefore, the address of the start 0f the next pollingmessage in the address column 00 of the buffer is still available whenthe adapter returns to the transmit state.

With the next CAT pulse from the DTT unit 14, the next character in thebuffer is placed in the information register and made available to theadapter over the DC lines. This normally would be an EOT characterforming the start of the next polling message stored in the buffer.However, the character may not be an EOT but a Group Mark, as pointedout in connection with the operation ovv diagram of FIG. 4, signalingthat the last polling message in the buffer has been sent. The GroupMark must `be examined to determine whether it is a text Group Mark orcontrol Group Mark. lf it is a text Group Mark, the buifer address isreset back to the initial address and the polling is repeated.Otherwise, the adapter returns to idle and the system is alerted by anInterrupt.

Considering first the condition where the rst character in the poll isnot a Group Mark and referring to FIG. 6 and the waveforms of FIG. 11,the SELF iiip-tiop 158 is turned olf during DTWS time by the output ofan AND circuit 196 which senses that the ENDF tiip-flop 144 is off andthat the character sensed by the decoder 146 is not a POL or an ENQ.This returns the adapter to the idle state. Also the TIMF Hip-flop 166is turned off during DTWS time `by the output of an AND circuit 198which senses that the adapter is in the poll state as indicated by theEOTF and SEL lines, that the character is f not ENQ and the ENDF ip-op144 is offf Operation of the polling message now continues with thesending of the address characters, the POL character, and the ENQcharacter in the manner described above.

The polling continues on successive polling messages in this manneruntil either a positive response to a poll is received or the lastpolling message in the buffer is transmitted. The last polling messageis followed by a Group Mark in the control state or followed by aNot-Equal character and a Group Mark to indicate a text state. The scharacter, when encountered in the buffer during transmission, signalsthe adapter to change states.

Operation of the adapter in the poll state when a text Group Mark isencountered is shown by the waveforms of FIG. l2. The sixabit eecharacter (01H10), when in the information register of the DTT unit 14,activates the DNE line at the output of the decoder 146. See FIG. 6. TheDNE level is used to complement the TEXF tiip-op 142 by means of an ANDcircuit 200 to which is applied the DTCD signal indicating that it isCAT time, the END' level indicating that it is not a message-endingcondition, and the DNE line. Since the TEXF ip-op 142 is normally in thecontrol state during the polling operation, a e character at this timecauses the ip-flop 142 to be cornplemented to the TEX state. At the sametime, a control ip-op 204, labeled SCIF, is turned on by the output ofthe AND circuit 200. The SCIF Hip-Hop 204 signals a mode change in theadapter. The output of the AND circuit 200 also turns on the ANNF ip-op116 to signal attention-needed.

The output of the AND circuit 200 is also applied to the BKC line to theDTT unit 14. This level, during the transmit state, operates the same inthe DTT unit 14 during CAT time as the discard signal DIC except thatthe address is permitted to increment so that the address now points tothe next character location in the buffer, rather than pointing at thesame character address, as in the case of the DIC discard. As a result,at the next CAT time of the DTT unit 14, the next character, which underthe case in consideration is a Group Mark, is placed in the informationregister, producing a signal on the GMK line from the decoder 146 in theadapter. The SCIF` flipop 204 is turned off by the DTCD, permitting theSELF flip-flop to be turned ofP iby the output of AND circuit 196 atDTWS time. Also at DTCD time, the DIC line to the DTT unit 14 is madetrue by the output of AND circuit 176. The DTT unit 14 is also reset `bythe RES line to which the output of an AND circuit 205 is connected. TheAND circuit 205 senses DTCD time, the GMK condition, the TEX or textstate condition, and the first poll character condition FIPL from an ANDcircuit 207. The latter senses the poll state, EOTF and SEL, and theEND' and LOC' are true. The output of the AND circut 205 also resets theTEXF ip-'lop 142 to the off or control state condition. The DTT unit 14and the adapter are now in condition to repeat the polling processstarting with the first polling message in the buffer.

If the Group Mark is encountered in the control state, the pollingoperation is discontinued and an Interrupt is sent to the system. Thisoperation is shown by the waveforms of FIG. 13. The same result can beinitiated by the processor via an Interrogate signal on a DPX line tothe adapter. A signal on a DPX line to the adapter turns on a DPXF ip-op212, signaling that the next negative poll response should stop theautomatic polling operation.

Assuming the first character following the EOT poll response is theGroup Mark, the adapter is still in the control state with the TEXFHip-nop 142 turned ofi The output of the AND circuit 207, designatedFIPL, indicates at this time that it is the rst character of the poll.FIPL is applied to an AND circuit 214 together with the group GMK linefrom the decoder 146 and the TEX line, indicating that the adapter is inthe control state, and the DTCD line, indicating that it is CAT time.The output of the AND circuit 214 provides a signal, designated EIR, tothe DTT unit 14, signaling that an end of input is recognized. Thisreturns the DTT unit 14 to the system, in the manner described in theabove-identified patent. The SELF ip-op 158 is reset to the "0 state,returning the adapter to the idle condition by the output of the ANDcircuit 196. The TRSF ip-op 114 is reset to place the adapter in thereceive state `by the EIR signal.

The polling operation can also be terminated by an interrogation fromthe processor which causes the DTT unit 14 to provide an output level ona DPX line. This sets a DPXF flip-flop 212 in the designated adapter. AnAND circuit 216 senses the DPXF state of the flip-op 212 and the DTCDpulse at CAT time and also the output FIPL of the AND circuit 207,indicating that it is the rst character in the poll. The AND circuit 216also produces a signal on the EIR line to the DTT unit 14. Thisterminates the polling operation, returning the butter to the system andplacing the adapter in the receive state and in the idle state. Thiscompletes the automatic polling description.

If a positive poll response is received from the remote station inresponse to a polling message, the rst character received from theremote station would not be an EOT but normally would be either an SOHcharacter, indicating the start of a heading, or an STX character,indicating the start of a text message. Since these are both controlcharacters, after they are stored in the information register of theDTI' unit 14, they are examined by the adapter at CAT time and modifiedfor storage in the buffer memory as a sixbit character. This requiresthat the sixth bit be complemented and the seventh bit be deleted.Referring again to FIG. 7, this is accomplished by the output of an ANDcircuit 230 to which is applied the DRCD pulse at the start of CAT time,the SCI state from the SCIF tlip-op 204 indicating that there has beenno mode change by the TEXF ilip-op 142, the DIC level indicating that nodiscard signal is being sent to the DTT' unit 14 in response to thepresence of a Tilde Underline or Delete (DEL) character, the TEX' levelindicating that the adapter is in the control state, and the A' levelfrom the decoder 146 indicating that the character is not a Circumex (A)character. The output of the AND circuit 230 is applied to gates 232 and234. Gate 232 gates the DC1 5 lines to the AC1 5 lines while the gate234 gates the DCs to the ACG. The output of the AND circuit 230 alsoprovides an ARC signal, signaling the DTT unit 14 that the adapter isreplacing the character in the information register.

The next character received after an SOH or STX control characternormally would be a text character requiring a mode change in theadapter and the insertion of a v character in the butler memory to agthe system that a mode change has taken place and that the nextcharacter is a text character. Again referring to FIG. 7 and inconnection with the timing diagram of FIG. 14, when the seventh bit ofthe received character is in the BlTF ip-tlop 122 and the rst six bitsof the received character are stored in the information register of theDTT unit 14, an AND circuit 240 senses that the seventh BAT is receivedby the adapter by sensing that the DC1' line is true, the DCZ' line istrue, and that the DC3 line is true. At the same time, a gating circuit242 looks at the condition of the TEXF ip-op 142 to determine if theadapter is in the control or text state and it looks at the bit storedin the BITF tlipflop 122. The gating circuit 242 also looks at theoutput of a decoder 244 which senses whether or not the rst six bitsstored in the information register of the DTT unit 14 together with theseventh bit in the BITE flip-flop 122 form the seven-bit codecombinations corresponding to the Circumex (A) character, the Tildecharacter, the Underline character, or the Delete (DEL) character. lfnone of these four characters is present and if a text character ispresent when the adapter is in the control state, or a control characteris present when the adapter is in the text state, as indicated by theTEXF flip-op 142, the output of the gating circuit, designated DSN, istrue, indicating that a mode change must take place.

The output of the gating circuit 242 is used to turn on the SCIFflip-flop 204. This is accomplished by the output of an AND circuit 246which senses that BAT-7 is true, that the DSN line is true, and that theTRS' line is true. This causes the attention-needed ip-op 116 to beturned on by the output of an AND circuit 248 to which the TRS' line isapplied and the SCI line is applied, indicating that the flip-flop 204has been turned on. The output of the AND circuit 248 also applies asignal to the CAM line going to the DTT unit 14, indicating a characteraccess operation. This results in a CAT signal being sent back by theDTT unit 14, producing a DRCD signal in the adapter.

A g character (01H10) is now applied to the AC lines going to the DTunit 14. This is accomplished by an AND circuit 250 which senses thatthe SCI condition is true, that the DIC' condition is true, indicatingthat no character discard is in order, and that the DRCD pulse ispresent at CAT time. The output of the AND circuit 250 is applied to agate 252 for gating the 7e character to the ACn lines. The output of theAND circuit 250 also applies to the signal of the ARC line, indicating acharacter replacement operation in the DTT unit 14. The output of theAND circuit 250 is also used to complement the TEXF ip-op 142. The SCIFHip-Hop 204 is turned off by the DRCD pulse. In this manner, the adapteris changed from the control mode to the text mode and a 7e character isinserted in the buffer memory to flag the mode change to the system.After the 5 character is stored in the buffer at the next addresslocation by the ARC signal, the remaining Parity bit and Stop bit of thecharacter being received are added to the character in the I/O sectionof the buffer in the normal manner. A CAT signal is then produced by theDTT unit 14, and unless the character is a Tilde, Underline, Delete orCircumex character, it is stored in the next location in the buffermemory.

lf the character received is a Tilde, an Underline, or

a Delete character, it cannot be transmitted or received and so isdiscarded if received and the TEXF ip-op 142 is not complemented. Tothis end, an AND circuit 254 at DRCD time senses whether either theTilde, Underline, or Delete characters are present at the output of thedecoder 146 and provides a signal on the DIC line to the DTT unit 14.This also inhibits the output of the AND circuit 250, preventing theTEXF Hip-Hop 142 from being complemented and preventing any mode changefrom taking place in the adapter.

If a Circumflex (A) character has been received, the g character is notinserted at BAT-7 time and no mode change takes place. After receipt ofthe Parity bit and the Stop bit has been completed in the normal manner,a character is inserted in the buffer memory. This is accomplished bythe normal storing of the six bits of the Circumex character which arethe same as the 7e character in the six-bit code. The output of the ANDcircuit 230 is false so that the sixth bit is not complemented. Also atthe same CAT time, an AND circuit 256 senses that the Circumex (A)character is present as determined by the decoder 146, turning on theSCIF Hip-flop 204 in response to the DRCD pulse, again indicating a modechange and complementing the TEXF ip-flop 142. Turning on the SCIFflip-Hop 204 causes a second g character to be inserted in the buffer.As a result the TEXF llip-op 142 is complemented a second time, with thenet result that no mode change takes place within the adapter, and theadapter is ready to receive the next character. In this manner, theCircumflex character is stored in the buffer memory as a pair of secharacters with no mode change taking place.

During transmission, as pointed out above, a 71: charater in the buffernormally flags a mode change between the text and control states. The secharacter is discarded and the next character is sent. If the nextcharacter is also a g character, a Circumtiex character is transmittedto the remote station. Since SCIF flip-flop is on when the secondcharacter is encountered at the next CAT time, the BKC line is not setand the character is transmitted and not discarded. The TEXF ip-op isagain complemented so that there is no net mode change of the adapter.The six-bit 9e character is now transmitted as a seven-bit Circumexcharacter by the adapter in the normal manner.

From the above description, it will be appreciated that a nonsynchronousadapter is provided which permits continuous polling of a number ofremote stations without any system interrupt to the processor forgenerating polling messages. A number of polling messages are loadedinto the buffer at one time by the processor, giving the systemflexibility and determining which remote stations will be polled and atwhat frequency they will be polled. For example, the polling messagescan be arranged in any manner desired so that one remote station can bepolled much more frequently than another remote station. The adapterpermits use of substantially the full ASCII code, permitting use ofupperand lower-case machines at the remote stations. The present adapterprovides the correct mapping capability for use with the Burroughs 5500computer systems. While the Tilde, Underline, and Delete characterscannot be transmitted or received, the Circumflex character can betransmitted or received by translating the seven-bit character to twosix-bit characters in the code conversion.

What is claimed is:

1. In a data transmission system in which an addressable buffer memorytransmits data to and receives data from a plurality of remote stationsover a communication line through a common line adapter circuit,apparatus for continuously polling the remote stations in anypredetermined order and frequency, comprising means in the adaptercoupling the buffer memory to the communication line for transferringcharacters between the buffer memory and communication line, means inthe adapter initating transfer by said transferring means of a sequenceof characters from the buffer memory to the remote stations startingwith a first predetermined address location, said sequence of charactersincluding a plurality of polling messages, each message havingcharacters identifying the address of a particular remote station,signaling a polling operation to the remote stations, and identifyingthe end of each polling message, lirst decoding means in the adaptercoupled to the transferring means for decoding each character as it istransferred to the communication line, said first decoding meanssignaling when the end of the polling message character is transferredout of memory, means responsive to the signal from said first decodingmeans for interrupting transfer of characters from the buffer memory tothe communication line by said transferring means, means coupled to thecommunication line for receiving coded characters from the remotestations, and second decoding means in the adapter coupled to the outputof said receiving means and responsive to a predetermined character froma remote station signaling that the remote station has no message forreactivating said transferring means to initiate transfer of the nextcharacters in said sequence from the buffer memory to the remotestation.

2. Apparatus as defined in claim 1, further including means in theadapter coupled to the output of the receiving means and responsive tomessage characters received from any polled remote station for loadingsaid message characters into the buffer memory starting with said rstpredetermined address location in memory.

3. Apparatus as defined in claim 1, further including means in theadapter coupled to said transferring means and responsive to firstpredetermined control characters when encountered in said sequence forinhibiting the transmission of said first control characters andresetting said transmitting means to said first predetermined address,whereby transfer of said sequence of characters is repeated.

4. Apparatus as defined in claim l, further including means in theadapter coupled to said transferring means and responsive to secondpredetermined control characters when encountered in said sequence forinhibiting the transmission of said second control characters andhalting further transfer of said sequence of characters from the buffermemory.

5. Apparatus for transmitting digital data to and receiving digital datafrom a plurality of remote stations over a common communication line,comprising an addressable memory having a plurality of polling messagesstored therein at predetermined address locations, each polling messageincluding coded characters identifying a particular remote station andsignaling a request for data transfer, means connected to the memory forreading out said polling message characters in sequence from saidpredetermined address locations starting with an initial address, meanscoupled to the output of the memory for transmitting the identifyingcharacters and the data request characters read out of memory to theremote stations, said transmitting means including decoding meansresponsive to the last character in each polling message forinterrupting said readout rneans and waiting for a reponse, meanscoupled to the communication line for receiving characters on the linefrom the remote stations, means coupled to the output of said receivingmeans for decoding any received characters, and connected to saiddecoding means responsive to predetermined characters when received froma remote station for reactivating said readout means, whereby the nextpolling message in address sequence is transmitted to the remotestations, means coupled to the memory readout means and responsive to apredetermined character read out of memory for iuhibiting transmissionof said character and resetting said memory readout means to the initialaddress, whereby the reading out of said polling messages is repeated.

6. Apparatus as defined in claim 5, further including means coupled tothe receiving means for storing characters received from a remotestation in the buffer memory,

said reactivating means responsive to said predetermined charactersinhibiting said character storing means when said predeterminedcharacters are received from the remote stations.

7. Apparatus as defined in claim 6, wherein said storing means includesmeans for storing the received characters in sequence in the buffermemory in said predetermined address locations starting with the initialaddress, whereby the received message from the remote station replacesthe polling messages in the memory.

8. Apparatus as defined in claim 5, further including means responsiveto the decoding means when a particular character is encountered forindicating that the said character has been read out of memory andinhibiting the transmission of said character to the remote station, andmeans responsive to the decoding means when said particular character isagain encountered as the next character in sequence read out of memoryand the indicating means has been previously set by encountering the rstone of said characters for transmitting a single character to the remotestation.

9. Apparatus as defined in claim 6, further including means responsiveto a particular character when received from a remote station forstoring a character in two successive address locations in the buffermemory.

References Cited UNITED STATES PATENTS 3,390,379 6/1968 Carlson et al340-1725 3,407,387 10/1968 Looschen et al 340-152 3,427,590 2/1969Mauzey et al 340-147 RAULFE B. ZACH, Primary Examiner

